一、GPU硬件接口信号设计

1、电源接口信号：P12V、P3V3、P3V3_STBY

电源部分通常会给出明确的电压、电流、ripple（纹波）、noise（噪声）、trainsient和时序等要求

A100 PCIe卡电压值要求：

A100 PCIe卡电流值要求：

电源接口信号：P12V、P3V3、P3V3_STBY

PCIe卡金手指最大电流值：

2、时钟信号：REFCK+\REFCLK-

The nominal single-ended swing for each clock is 0 V to 0.7 V and a nominal frequency of 100 MHz ±300 PPM. The reference clock distribution to all devices must be matched to within 15 inches.The transport delay delta between the data and clock at the Receiver must be less than 12 ns.

The PCIe reference clock between the A100 PCIe card and its upstream link partner must be a common clock.SRIS/SRNS clocking schemes are not supported. PCIe spec compatible spread-spectrum clocking(SSC) is supported.

3、PCIe reset信号

The PERST# signal is used to indicate when the power supply is within its specified voltage tolerance and  is stable. It also initializes a component state machines and other logic once power supplies stabilize. On power-up, the de-assertion of PERST# is delayed 100 ms from the power rails achieving  specified operating limits. Also, within this time, the reference clocks (REFCLK+, REFCLK-) also become stable.

4、Wake#信号（optional）

The WAKE# signal is an open drain, active low signal that is driven low by a PCI Express Add-in Card to reactivate the PCI Express slot main power rails and reference clocks. Wake信号被触发可以唤醒服务器整机。

5、SMBUs信号（optional）

SMBus provides a control bus for system and power management related tasks. With SMBus, a device can provide manufacturer information, tell the system what its model/part number is, save its state for a suspend event, report different types of errors, accept control parameters, and return its status.

An out-of-band channel exists through the SMBus Post-Box Interface protocol to set the power limit of the GPU，using SMBPBI,the configured power limit setting can be made persistent across driver reloads.

6、Power Brake

The power brake feature allows the systems to trigger hardware slowdown in the GPU with the external input.For example,the system can assert Power Brake during an emergency power or thermal event.Note that the Power Brake should not be used as a way to dynamically control the power consumption of the GPU . That is,Power Brake is intended for emergency power reduction purpose only.

The system can assert Power Brake signal (PB#) via Pin B30 on the PCIe edge connector.The typical response time as seen at the system power supplies after assertion is noted in below table.

7、CLKREQ#

The A100 PCIe card outputs the PCIe Clock Request（CLKREQ#） signal on PCIe Pin B12 to signal to the host when the PCIe reference clock is needed.

The A100 PCIe card asserts CLKREQ# low during normal operation when the PCIe REFCLK is needed.The card deasserts CLKREQ#  high when it  enters a low power state and the PCIe REFCLK is not needed and asserts CLKREQ# low when exiting a low power state.

8、PRSNT#

BMC或CPLD通过检测该信号来判断GPU卡是否安装到了机器上。

9、PCIe信号

PCIe信号在板子上走线时，需要严格控制走线策略、线间距、长度差等。比如一组差分信号走线时，PN信号在每一层和总的走线长度上需要保持<=5 mils范围内，1 inch=2.54cm，1mil=1/1000 inch=0.0254mm

PCIe lane Reversal、PN Inversion：Lane Polarity Inversion and Lane Reversal is supported on the A 100 PCIe card.